Bus topology calculation.
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@ -262,6 +262,11 @@ int ec_cdev_ioctl_slave(
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data.ports[i].dl_loop = slave->ports[i].dl_loop;
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data.ports[i].dl_signal = slave->ports[i].dl_signal;
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data.dc_receive_times[i] = slave->dc_receive_times[i];
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if (slave->next_slave[i]) {
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data.next_slave[i] = slave->next_slave[i]->ring_position;
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} else {
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data.next_slave[i] = 0xffff;
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}
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}
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data.fmmu_bit = slave->base_fmmu_bit_operation;
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data.dc_supported = slave->base_dc_supported;
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@ -867,6 +867,9 @@ void ec_fsm_master_state_scan_slave(
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// find DC reference clock
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ec_master_find_dc_ref_clock(master);
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// calculate bus topology
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ec_master_calc_topology(master);
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// Attach slave configurations
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ec_master_attach_slave_configs(master);
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@ -167,6 +167,7 @@ typedef struct {
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int16_t current_on_ebus;
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ec_slave_port_desc_t port_descs[EC_MAX_PORTS];
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ec_slave_port_t ports[EC_MAX_PORTS];
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uint16_t next_slave[EC_MAX_PORTS];
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uint8_t fmmu_bit;
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uint8_t dc_supported;
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ec_slave_dc_range_t dc_range;
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@ -1373,6 +1373,57 @@ void ec_master_find_dc_ref_clock(
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ec_datagram_frmw(&master->sync_datagram, ref_clock_addr, 0x0910, 4);
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}
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/*****************************************************************************/
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/** Calculates the bus topology; recursion function.
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*/
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int ec_master_calc_topology_rec(
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ec_master_t *master, /**< EtherCAT master. */
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ec_slave_t *port0_slave, /**< Slave at port 0. */
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unsigned int *slave_position /**< Slave position. */
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)
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{
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ec_slave_t *slave = master->slaves + *slave_position;
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unsigned int i;
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int ret;
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slave->next_slave[0] = port0_slave;
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for (i = 1; i < EC_MAX_PORTS; i++) {
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if (!slave->ports[i].dl_loop) {
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*slave_position = *slave_position + 1;
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if (*slave_position < master->slave_count) {
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slave->next_slave[i] = master->slaves + *slave_position;
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ret = ec_master_calc_topology_rec(master,
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slave, slave_position);
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if (ret)
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return ret;
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} else {
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return -1;
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}
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}
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}
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return 0;
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}
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/*****************************************************************************/
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/** Calculates the bus topology.
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*/
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void ec_master_calc_topology(
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ec_master_t *master /**< EtherCAT master. */
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)
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{
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unsigned int slave_position = 0;
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if (master->slave_count == 0)
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return;
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if (ec_master_calc_topology_rec(master, NULL, &slave_position))
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EC_ERR("Failed to calculate bus topology.\n");
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}
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/******************************************************************************
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* Application interface
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*****************************************************************************/
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@ -234,6 +234,7 @@ ec_slave_config_t *ecrt_master_slave_config_err(ec_master_t *, uint16_t,
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uint16_t, uint32_t, uint32_t);
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void ec_master_find_dc_ref_clock(ec_master_t *);
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void ec_master_calc_topology(ec_master_t *);
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/*****************************************************************************/
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@ -97,6 +97,8 @@ void ec_slave_init(
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slave->sii.physical_layer[i] = 0xFF;
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slave->dc_receive_times[i] = 0U;
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slave->next_slave[i] = NULL;
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}
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slave->base_fmmu_bit_operation = 0;
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@ -131,6 +131,7 @@ struct ec_slave
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// data link status
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ec_slave_port_t ports[EC_MAX_PORTS]; /**< Port link status. */
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ec_slave_t *next_slave[EC_MAX_PORTS]; /**< Connected slaves. */
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// SII
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uint16_t *sii_words; /**< Complete SII image. */
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@ -266,7 +266,7 @@ void CommandSlaves::showSlaves(
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cout << "no" << endl;
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}
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cout << "Port Type Link Loop Signal";
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cout << "Port Type Link Loop Signal NextSlave";
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if (si->dc_supported)
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cout << " RxTime Diff";
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cout << endl;
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@ -294,11 +294,18 @@ void CommandSlaves::showSlaves(
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<< (si->ports[i].dl_link ? "up" : "down")
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<< " " << setw(6)
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<< (si->ports[i].dl_loop ? "closed" : "open")
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<< " " << setw(3)
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<< (si->ports[i].dl_signal ? "yes" : "no");
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<< " " << setw(6)
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<< (si->ports[i].dl_signal ? "yes" : "no")
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<< " " << setw(9) << right;
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if (si->next_slave[i] != 0xffff) {
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cout << dec << si->next_slave[i];
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} else {
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cout << "-";
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}
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if (si->dc_supported) {
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cout << " " << setw(10) << right;
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cout << " " << setw(10) << right;
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if (si->ports[i].dl_signal) {
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cout << dec << si->dc_receive_times[i];
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} else {
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