reorder functions in update.c to omit forward declarations
This commit is contained in:
Patrick Bruenn
parent
2f4a4fd5fe
commit
b1214f2548
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@ -57,13 +57,6 @@ struct update_buffer {
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size_t size;
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};
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static void ccat_wait_status_cleared(void __iomem * const ioaddr);
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static int ccat_read_flash(void __iomem * const ioaddr, char __user * buf,
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u32 len, loff_t * off);
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static void ccat_write_flash(const struct update_buffer *const buf);
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static void ccat_update_cmd(void __iomem * const ioaddr, u8 cmd, u16 clocks);
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static void ccat_update_destroy(struct kref *ref);
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/**
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* wait_until_busy_reset() - wait until the busy flag was reset
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* @ioaddr: address of the CCAT Update function in PCI config space
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@ -76,6 +69,215 @@ static inline void wait_until_busy_reset(void __iomem * const ioaddr)
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}
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}
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/**
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* __ccat_update_cmd() - Helper to issue a FPGA flash command
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* @ioaddr: address of the CCAT Update function in PCI config space
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* @cmd: the command identifier
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* @clocks: the number of clocks associated with the specified command
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*
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* no write memory barrier is called and the busy flag is not evaluated
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*/
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static inline void __ccat_update_cmd(void __iomem * const ioaddr, u8 cmd,
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u16 clocks)
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{
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iowrite8((0xff00 & clocks) >> 8, ioaddr);
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iowrite8(0x00ff & clocks, ioaddr + 0x8);
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iowrite8(cmd, ioaddr + 0x10);
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}
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/**
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* ccat_update_cmd() - Helper to issue a FPGA flash command
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* @ioaddr: address of the CCAT Update function in PCI config space
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* @cmd: the command identifier
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* @clocks: the number of clocks associated with the specified command
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*
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* Triggers a full flash command cycle with write memory barrier and
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* command activate. This call blocks until the busy flag is reset.
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*/
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static inline void ccat_update_cmd(void __iomem * const ioaddr, u8 cmd,
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u16 clocks)
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{
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__ccat_update_cmd(ioaddr, cmd, clocks);
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wmb();
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iowrite8(0xff, ioaddr + 0x7f8);
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wait_until_busy_reset(ioaddr);
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}
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/**
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* ccat_update_cmd_addr() - Helper to issue a FPGA flash command with address parameter
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* @ioaddr: address of the CCAT Update function in PCI config space
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* @cmd: the command identifier
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* @clocks: the number of clocks associated with the specified command
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* @addr: 24 bit address associated with the specified command
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*
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* Triggers a full flash command cycle with write memory barrier and
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* command activate. This call blocks until the busy flag is reset.
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*/
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static inline void ccat_update_cmd_addr(void __iomem * const ioaddr,
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u8 cmd, u16 clocks, u32 addr)
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{
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const u8 addr_0 = SWAP_BITS(addr & 0xff);
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const u8 addr_1 = SWAP_BITS((addr & 0xff00) >> 8);
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const u8 addr_2 = SWAP_BITS((addr & 0xff0000) >> 16);
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__ccat_update_cmd(ioaddr, cmd, clocks);
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iowrite8(addr_2, ioaddr + 0x18);
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iowrite8(addr_1, ioaddr + 0x20);
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iowrite8(addr_0, ioaddr + 0x28);
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wmb();
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iowrite8(0xff, ioaddr + 0x7f8);
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wait_until_busy_reset(ioaddr);
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}
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/**
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* ccat_get_status() - Read CCAT Update status
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* @ioaddr: address of the CCAT Update function in PCI config space
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*
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* Return: the current status of the CCAT Update function
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*/
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static u8 ccat_get_status(void __iomem * const ioaddr)
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{
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ccat_update_cmd(ioaddr, CCAT_READ_STATUS);
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return ioread8(ioaddr + 0x20);
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}
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/**
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* ccat_read_flash_block() - Read a block of CCAT configuration data from flash
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* @ioaddr: address of the CCAT Update function in PCI config space
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* @addr: 24 bit address of the block to read
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* @len: number of bytes to read from this block, len <= CCAT_DATA_BLOCK_SIZE
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* @buf: output buffer in user space
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*
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* Copies one block of configuration data from the CCAT FPGA's flash to
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* the user space buffer.
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* Note that the size of the FPGA's firmware is not known exactly so it
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* is very possible that the overall buffer ends with a lot of 0xff.
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*
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* Return: the number of bytes copied
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*/
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static int ccat_read_flash_block(void __iomem * const ioaddr,
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const u32 addr, const u16 len,
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char __user * const buf)
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{
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u16 i;
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const u16 clocks = 8 * len;
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ccat_update_cmd_addr(ioaddr, CCAT_READ_FLASH + clocks, addr);
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for (i = 0; i < len; i++) {
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put_user(ioread8(ioaddr + CCAT_DATA_IN_4 + 8 * i), buf + i);
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}
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return len;
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}
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/**
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* ccat_read_flash() - Read a chunk of CCAT configuration data from flash
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* @ioaddr: address of the CCAT Update function in PCI config space
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* @buf: output buffer in user space
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* @len: number of bytes to read
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* @off: offset in the configuration data
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*
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* Copies multiple blocks of configuration data from the CCAT FPGA's
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* flash to the user space buffer.
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*
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* Return: the number of bytes copied
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*/
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static int ccat_read_flash(void __iomem * const ioaddr, char __user * buf,
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u32 len, loff_t * off)
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{
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const loff_t start = *off;
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while (len > CCAT_DATA_BLOCK_SIZE) {
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*off +=
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ccat_read_flash_block(ioaddr, *off, CCAT_DATA_BLOCK_SIZE,
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buf);
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buf += CCAT_DATA_BLOCK_SIZE;
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len -= CCAT_DATA_BLOCK_SIZE;
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}
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*off += ccat_read_flash_block(ioaddr, *off, len, buf);
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return *off - start;
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}
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/**
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* ccat_wait_status_cleared() - wait until CCAT status is cleared
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* @ioaddr: address of the CCAT Update function in PCI config space
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*
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* Blocks until bit 7 of the CCAT Update status is reset
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*/
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static void ccat_wait_status_cleared(void __iomem * const ioaddr)
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{
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u8 status;
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do {
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status = ccat_get_status(ioaddr);
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} while (status & (1 << 7));
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}
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/**
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* ccat_write_flash_block() - Write a block of CCAT configuration data to flash
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* @ioaddr: address of the CCAT Update function in PCI config space
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* @addr: 24 bit start address in the CCAT FPGA's flash
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* @len: number of bytes to write in this block, len <= CCAT_WRITE_BLOCK_SIZE
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* @buf: input buffer
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*
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* Copies one block of configuration data to the CCAT FPGA's flash
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*
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* Return: the number of bytes copied
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*/
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static int ccat_write_flash_block(void __iomem * const ioaddr,
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const u32 addr, const u16 len,
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const char *const buf)
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{
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const u16 clocks = 8 * len;
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u16 i;
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ccat_update_cmd(ioaddr, CCAT_WRITE_ENABLE);
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for (i = 0; i < len; i++) {
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iowrite8(buf[i], ioaddr + CCAT_DATA_OUT_4 + 8 * i);
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}
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ccat_update_cmd_addr(ioaddr, CCAT_WRITE_FLASH + clocks, addr);
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ccat_wait_status_cleared(ioaddr);
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return len;
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}
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/**
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* ccat_write_flash() - Write a new CCAT configuration to FPGA's flash
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* @update: a CCAT Update buffer containing the new FPGA configuration
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*/
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static void ccat_write_flash(const struct update_buffer *const update)
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{
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const char *buf = update->data;
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u32 off = 0;
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size_t len = update->size;
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while (len > CCAT_WRITE_BLOCK_SIZE) {
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ccat_write_flash_block(update->update->ioaddr, off,
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(u16) CCAT_WRITE_BLOCK_SIZE, buf);
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off += CCAT_WRITE_BLOCK_SIZE;
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buf += CCAT_WRITE_BLOCK_SIZE;
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len -= CCAT_WRITE_BLOCK_SIZE;
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}
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ccat_write_flash_block(update->update->ioaddr, off, (u16) len, buf);
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}
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/**
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* ccat_update_destroy() - Cleanup the CCAT Update function
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* @ref: pointer to a struct kref embedded into a struct ccat_update, which we intend to destroy
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*
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* Retrieves the parent struct ccat_update and destroys it.
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*/
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static void ccat_update_destroy(struct kref *ref)
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{
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struct ccat_update *update =
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container_of(ref, struct ccat_update, refcount);
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cdev_del(&update->cdev);
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device_destroy(update->class, update->dev);
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class_destroy(update->class);
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unregister_chrdev_region(update->dev, 1);
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kfree(update);
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pr_debug("%s(): done\n", __FUNCTION__);
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}
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static int ccat_update_open(struct inode *const i, struct file *const f)
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{
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struct ccat_update *update =
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@ -183,66 +385,6 @@ static struct file_operations update_ops = {
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.write = ccat_update_write,
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};
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/**
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* __ccat_update_cmd() - Helper to issue a FPGA flash command
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* @ioaddr: address of the CCAT Update function in PCI config space
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* @cmd: the command identifier
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* @clocks: the number of clocks associated with the specified command
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*
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* no write memory barrier is called and the busy flag is not evaluated
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*/
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static inline void __ccat_update_cmd(void __iomem * const ioaddr, u8 cmd,
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u16 clocks)
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{
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iowrite8((0xff00 & clocks) >> 8, ioaddr);
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iowrite8(0x00ff & clocks, ioaddr + 0x8);
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iowrite8(cmd, ioaddr + 0x10);
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}
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/**
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* ccat_update_cmd() - Helper to issue a FPGA flash command
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* @ioaddr: address of the CCAT Update function in PCI config space
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* @cmd: the command identifier
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* @clocks: the number of clocks associated with the specified command
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*
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* Triggers a full flash command cycle with write memory barrier and
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* command activate. This call blocks until the busy flag is reset.
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*/
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static inline void ccat_update_cmd(void __iomem * const ioaddr, u8 cmd,
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u16 clocks)
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{
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__ccat_update_cmd(ioaddr, cmd, clocks);
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wmb();
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iowrite8(0xff, ioaddr + 0x7f8);
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wait_until_busy_reset(ioaddr);
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}
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/**
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* ccat_update_cmd_addr() - Helper to issue a FPGA flash command with address parameter
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* @ioaddr: address of the CCAT Update function in PCI config space
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* @cmd: the command identifier
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* @clocks: the number of clocks associated with the specified command
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* @addr: 24 bit address associated with the specified command
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*
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* Triggers a full flash command cycle with write memory barrier and
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* command activate. This call blocks until the busy flag is reset.
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*/
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static inline void ccat_update_cmd_addr(void __iomem * const ioaddr,
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u8 cmd, u16 clocks, u32 addr)
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{
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const u8 addr_0 = SWAP_BITS(addr & 0xff);
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const u8 addr_1 = SWAP_BITS((addr & 0xff00) >> 8);
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const u8 addr_2 = SWAP_BITS((addr & 0xff0000) >> 16);
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__ccat_update_cmd(ioaddr, cmd, clocks);
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iowrite8(addr_2, ioaddr + 0x18);
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iowrite8(addr_1, ioaddr + 0x20);
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iowrite8(addr_0, ioaddr + 0x28);
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wmb();
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iowrite8(0xff, ioaddr + 0x7f8);
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wait_until_busy_reset(ioaddr);
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}
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/**
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* ccat_get_prom_id() - Read CCAT PROM ID
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* @ioaddr: address of the CCAT Update function in PCI config space
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@ -255,136 +397,6 @@ u8 ccat_get_prom_id(void __iomem * const ioaddr)
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return ioread8(ioaddr + 0x38);
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}
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/**
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* ccat_get_status() - Read CCAT Update status
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* @ioaddr: address of the CCAT Update function in PCI config space
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*
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* Return: the current status of the CCAT Update function
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*/
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static u8 ccat_get_status(void __iomem * const ioaddr)
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{
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ccat_update_cmd(ioaddr, CCAT_READ_STATUS);
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return ioread8(ioaddr + 0x20);
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}
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/**
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* ccat_wait_status_cleared() - wait until CCAT status is cleared
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* @ioaddr: address of the CCAT Update function in PCI config space
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*
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* Blocks until bit 7 of the CCAT Update status is reset
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*/
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static void ccat_wait_status_cleared(void __iomem * const ioaddr)
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{
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u8 status;
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do {
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status = ccat_get_status(ioaddr);
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} while (status & (1 << 7));
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}
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/**
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* ccat_read_flash_block() - Read a block of CCAT configuration data from flash
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* @ioaddr: address of the CCAT Update function in PCI config space
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* @addr: 24 bit address of the block to read
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* @len: number of bytes to read from this block, len <= CCAT_DATA_BLOCK_SIZE
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* @buf: output buffer in user space
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*
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* Copies one block of configuration data from the CCAT FPGA's flash to
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* the user space buffer.
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* Note that the size of the FPGA's firmware is not known exactly so it
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* is very possible that the overall buffer ends with a lot of 0xff.
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*
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* Return: the number of bytes copied
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*/
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static int ccat_read_flash_block(void __iomem * const ioaddr,
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const u32 addr, const u16 len,
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char __user * const buf)
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{
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u16 i;
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const u16 clocks = 8 * len;
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ccat_update_cmd_addr(ioaddr, CCAT_READ_FLASH + clocks, addr);
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for (i = 0; i < len; i++) {
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put_user(ioread8(ioaddr + CCAT_DATA_IN_4 + 8 * i), buf + i);
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}
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return len;
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}
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/**
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* ccat_read_flash() - Read a chunk of CCAT configuration data from flash
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* @ioaddr: address of the CCAT Update function in PCI config space
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* @buf: output buffer in user space
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* @len: number of bytes to read
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* @off: offset in the configuration data
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*
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* Copies multiple blocks of configuration data from the CCAT FPGA's
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* flash to the user space buffer.
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*
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* Return: the number of bytes copied
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*/
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static int ccat_read_flash(void __iomem * const ioaddr, char __user * buf,
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u32 len, loff_t * off)
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{
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const loff_t start = *off;
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while (len > CCAT_DATA_BLOCK_SIZE) {
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*off +=
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ccat_read_flash_block(ioaddr, *off, CCAT_DATA_BLOCK_SIZE,
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buf);
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buf += CCAT_DATA_BLOCK_SIZE;
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len -= CCAT_DATA_BLOCK_SIZE;
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}
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*off += ccat_read_flash_block(ioaddr, *off, len, buf);
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return *off - start;
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}
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/**
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* ccat_write_flash_block() - Write a block of CCAT configuration data to flash
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* @ioaddr: address of the CCAT Update function in PCI config space
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* @addr: 24 bit start address in the CCAT FPGA's flash
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* @len: number of bytes to write in this block, len <= CCAT_WRITE_BLOCK_SIZE
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* @buf: input buffer
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*
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* Copies one block of configuration data to the CCAT FPGA's flash
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*
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* Return: the number of bytes copied
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*/
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static int ccat_write_flash_block(void __iomem * const ioaddr,
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const u32 addr, const u16 len,
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const char *const buf)
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{
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const u16 clocks = 8 * len;
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u16 i;
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ccat_update_cmd(ioaddr, CCAT_WRITE_ENABLE);
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for (i = 0; i < len; i++) {
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iowrite8(buf[i], ioaddr + CCAT_DATA_OUT_4 + 8 * i);
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}
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ccat_update_cmd_addr(ioaddr, CCAT_WRITE_FLASH + clocks, addr);
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ccat_wait_status_cleared(ioaddr);
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return len;
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}
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/**
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* ccat_write_flash() - Write a new CCAT configuration to FPGA's flash
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* @update: a CCAT Update buffer containing the new FPGA configuration
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*/
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static void ccat_write_flash(const struct update_buffer *const update)
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{
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const char *buf = update->data;
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u32 off = 0;
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size_t len = update->size;
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while (len > CCAT_WRITE_BLOCK_SIZE) {
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ccat_write_flash_block(update->update->ioaddr, off,
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(u16) CCAT_WRITE_BLOCK_SIZE, buf);
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off += CCAT_WRITE_BLOCK_SIZE;
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buf += CCAT_WRITE_BLOCK_SIZE;
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len -= CCAT_WRITE_BLOCK_SIZE;
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}
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ccat_write_flash_block(update->update->ioaddr, off, (u16) len, buf);
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}
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/**
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* ccat_update_init() - Initialize the CCAT Update function
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*/
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@ -436,25 +448,6 @@ cleanup:
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return NULL;
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}
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/**
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* ccat_update_destroy() - Cleanup the CCAT Update function
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* @ref: pointer to a struct kref embedded into a struct ccat_update, which we intend to destroy
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*
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* Retrieves the parent struct ccat_update and destroys it.
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*/
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static void ccat_update_destroy(struct kref *ref)
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{
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struct ccat_update *update =
|
||||
container_of(ref, struct ccat_update, refcount);
|
||||
|
||||
cdev_del(&update->cdev);
|
||||
device_destroy(update->class, update->dev);
|
||||
class_destroy(update->class);
|
||||
unregister_chrdev_region(update->dev, 1);
|
||||
kfree(update);
|
||||
pr_debug("%s(): done\n", __FUNCTION__);
|
||||
}
|
||||
|
||||
/**
|
||||
* ccat_update_remove() - Prepare the CCAT Update function for removal
|
||||
*/
|
||||
|
|
|
|||
Loading…
Reference in New Issue