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ethercat
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Rescan command.

This commit is contained in:
Florian Pose 2010-09-16 09:08:11 +02:00
parent ab10c64764
commit 6f97d7e27f
11 changed files with 236 additions and 70 deletions
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1
TODO
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@ -13,7 +13,6 @@ Version 1.5.0:
* Ethernet drivers: * Ethernet drivers:
- Fix link detection in generic driver. - Fix link detection in generic driver.
- Add native drivers from 2.6.24 up to 2.6.31. - Add native drivers from 2.6.24 up to 2.6.31.
* Rescan command.
* Change SDO index at runtime for SDO request. * Change SDO index at runtime for SDO request.
* Output skipped datagrams again. * Output skipped datagrams again.
* Output warning when send_ext() is called in illegal context. * Output warning when send_ext() is called in illegal context.

17
master/cdev.c
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@ -659,6 +659,19 @@ int ec_cdev_ioctl_master_debug(
/*****************************************************************************/ /*****************************************************************************/
/** Issue a bus scan.
*/
int ec_cdev_ioctl_master_rescan(
ec_master_t *master, /**< EtherCAT master. */
unsigned long arg /**< ioctl() argument. */
)
{
master->fsm.rescan_required = 1;
return 0;
}
/*****************************************************************************/
/** Set slave state. /** Set slave state.
*/ */
int ec_cdev_ioctl_slave_state( int ec_cdev_ioctl_slave_state(
@ -3579,6 +3592,10 @@ long eccdev_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
if (!(filp->f_mode & FMODE_WRITE)) if (!(filp->f_mode & FMODE_WRITE))
return -EPERM; return -EPERM;
return ec_cdev_ioctl_master_debug(master, arg); return ec_cdev_ioctl_master_debug(master, arg);
case EC_IOCTL_MASTER_RESCAN:
if (!(filp->f_mode & FMODE_WRITE))
return -EPERM;
return ec_cdev_ioctl_master_rescan(master, arg);
case EC_IOCTL_SLAVE_STATE: case EC_IOCTL_SLAVE_STATE:
if (!(filp->f_mode & FMODE_WRITE)) if (!(filp->f_mode & FMODE_WRITE))
return -EPERM; return -EPERM;

11
master/fsm_master.c
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@ -85,7 +85,7 @@ void ec_fsm_master_init(
fsm->idle = 0; fsm->idle = 0;
fsm->link_state = 0; fsm->link_state = 0;
fsm->slaves_responding = 0; fsm->slaves_responding = 0;
fsm->topology_change_pending = 0; fsm->rescan_required = 0;
fsm->slave_states = EC_SLAVE_STATE_UNKNOWN; fsm->slave_states = EC_SLAVE_STATE_UNKNOWN;
// init sub-state-machines // init sub-state-machines
@ -201,7 +201,7 @@ void ec_fsm_master_state_broadcast(
// bus topology change? // bus topology change?
if (datagram->working_counter != fsm->slaves_responding) { if (datagram->working_counter != fsm->slaves_responding) {
fsm->topology_change_pending = 1; fsm->rescan_required = 1;
fsm->slaves_responding = datagram->working_counter; fsm->slaves_responding = datagram->working_counter;
EC_MASTER_INFO(master, "%u slave(s) responding.\n", EC_MASTER_INFO(master, "%u slave(s) responding.\n",
fsm->slaves_responding); fsm->slaves_responding);
@ -237,7 +237,7 @@ void ec_fsm_master_state_broadcast(
fsm->slave_states = 0x00; fsm->slave_states = 0x00;
} }
if (fsm->topology_change_pending) { if (fsm->rescan_required) {
down(&master->scan_sem); down(&master->scan_sem);
if (!master->allow_scan) { if (!master->allow_scan) {
up(&master->scan_sem); up(&master->scan_sem);
@ -245,9 +245,8 @@ void ec_fsm_master_state_broadcast(
master->scan_busy = 1; master->scan_busy = 1;
up(&master->scan_sem); up(&master->scan_sem);
// topology change when scan is allowed:
// clear all slaves and scan the bus // clear all slaves and scan the bus
fsm->topology_change_pending = 0; fsm->rescan_required = 0;
fsm->idle = 0; fsm->idle = 0;
fsm->scan_jiffies = jiffies; fsm->scan_jiffies = jiffies;
@ -630,7 +629,7 @@ void ec_fsm_master_state_read_state(
slave->error_flag = 1; slave->error_flag = 1;
EC_SLAVE_DBG(slave, 1, "Slave did not respond to state query.\n"); EC_SLAVE_DBG(slave, 1, "Slave did not respond to state query.\n");
} }
fsm->topology_change_pending = 1; fsm->rescan_required = 1;
ec_fsm_master_restart(fsm); ec_fsm_master_restart(fsm);
return; return;
} }

2
master/fsm_master.h
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@ -119,7 +119,7 @@ struct ec_fsm_master {
unsigned long scan_jiffies; /**< beginning of slave scanning */ unsigned long scan_jiffies; /**< beginning of slave scanning */
uint8_t link_state; /**< Last main device link state. */ uint8_t link_state; /**< Last main device link state. */
unsigned int slaves_responding; /**< number of responding slaves */ unsigned int slaves_responding; /**< number of responding slaves */
unsigned int topology_change_pending; /**< bus topology changed */ unsigned int rescan_required; /**< A bus rescan is required. */
ec_slave_state_t slave_states; /**< states of responding slaves */ ec_slave_state_t slave_states; /**< states of responding slaves */
ec_slave_t *slave; /**< current slave */ ec_slave_t *slave; /**< current slave */
ec_sii_write_request_t *sii_request; /**< SII write request */ ec_sii_write_request_t *sii_request; /**< SII write request */

125
master/ioctl.h
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@ -56,7 +56,7 @@
* *
* Increment this when changing the ioctl interface! * Increment this when changing the ioctl interface!
*/ */
#define EC_IOCTL_VERSION_MAGIC 6 #define EC_IOCTL_VERSION_MAGIC 7
// Command-line tool // Command-line tool
#define EC_IOCTL_MODULE EC_IOR(0x00, ec_ioctl_module_t) #define EC_IOCTL_MODULE EC_IOR(0x00, ec_ioctl_module_t)
@ -69,71 +69,72 @@
#define EC_IOCTL_DOMAIN_FMMU EC_IOWR(0x07, ec_ioctl_domain_fmmu_t) #define EC_IOCTL_DOMAIN_FMMU EC_IOWR(0x07, ec_ioctl_domain_fmmu_t)
#define EC_IOCTL_DOMAIN_DATA EC_IOWR(0x08, ec_ioctl_domain_data_t) #define EC_IOCTL_DOMAIN_DATA EC_IOWR(0x08, ec_ioctl_domain_data_t)
#define EC_IOCTL_MASTER_DEBUG EC_IO(0x09) #define EC_IOCTL_MASTER_DEBUG EC_IO(0x09)
#define EC_IOCTL_SLAVE_STATE EC_IOW(0x0a, ec_ioctl_slave_state_t) #define EC_IOCTL_MASTER_RESCAN EC_IO(0x0a)
#define EC_IOCTL_SLAVE_SDO EC_IOWR(0x0b, ec_ioctl_slave_sdo_t) #define EC_IOCTL_SLAVE_STATE EC_IOW(0x0b, ec_ioctl_slave_state_t)
#define EC_IOCTL_SLAVE_SDO_ENTRY EC_IOWR(0x0c, ec_ioctl_slave_sdo_entry_t) #define EC_IOCTL_SLAVE_SDO EC_IOWR(0x0c, ec_ioctl_slave_sdo_t)
#define EC_IOCTL_SLAVE_SDO_UPLOAD EC_IOWR(0x0d, ec_ioctl_slave_sdo_upload_t) #define EC_IOCTL_SLAVE_SDO_ENTRY EC_IOWR(0x0d, ec_ioctl_slave_sdo_entry_t)
#define EC_IOCTL_SLAVE_SDO_DOWNLOAD EC_IOWR(0x0e, ec_ioctl_slave_sdo_download_t) #define EC_IOCTL_SLAVE_SDO_UPLOAD EC_IOWR(0x0e, ec_ioctl_slave_sdo_upload_t)
#define EC_IOCTL_SLAVE_SII_READ EC_IOWR(0x0f, ec_ioctl_slave_sii_t) #define EC_IOCTL_SLAVE_SDO_DOWNLOAD EC_IOWR(0x0f, ec_ioctl_slave_sdo_download_t)
#define EC_IOCTL_SLAVE_SII_WRITE EC_IOW(0x10, ec_ioctl_slave_sii_t) #define EC_IOCTL_SLAVE_SII_READ EC_IOWR(0x10, ec_ioctl_slave_sii_t)
#define EC_IOCTL_SLAVE_REG_READ EC_IOWR(0x11, ec_ioctl_slave_reg_t) #define EC_IOCTL_SLAVE_SII_WRITE EC_IOW(0x11, ec_ioctl_slave_sii_t)
#define EC_IOCTL_SLAVE_REG_WRITE EC_IOW(0x12, ec_ioctl_slave_reg_t) #define EC_IOCTL_SLAVE_REG_READ EC_IOWR(0x12, ec_ioctl_slave_reg_t)
#define EC_IOCTL_SLAVE_FOE_READ EC_IOWR(0x13, ec_ioctl_slave_foe_t) #define EC_IOCTL_SLAVE_REG_WRITE EC_IOW(0x13, ec_ioctl_slave_reg_t)
#define EC_IOCTL_SLAVE_FOE_WRITE EC_IOW(0x14, ec_ioctl_slave_foe_t) #define EC_IOCTL_SLAVE_FOE_READ EC_IOWR(0x14, ec_ioctl_slave_foe_t)
#define EC_IOCTL_SLAVE_SOE_READ EC_IOWR(0x15, ec_ioctl_slave_soe_read_t) #define EC_IOCTL_SLAVE_FOE_WRITE EC_IOW(0x15, ec_ioctl_slave_foe_t)
#define EC_IOCTL_SLAVE_SOE_WRITE EC_IOWR(0x16, ec_ioctl_slave_soe_write_t) #define EC_IOCTL_SLAVE_SOE_READ EC_IOWR(0x16, ec_ioctl_slave_soe_read_t)
#define EC_IOCTL_CONFIG EC_IOWR(0x17, ec_ioctl_config_t) #define EC_IOCTL_SLAVE_SOE_WRITE EC_IOWR(0x17, ec_ioctl_slave_soe_write_t)
#define EC_IOCTL_CONFIG_PDO EC_IOWR(0x18, ec_ioctl_config_pdo_t) #define EC_IOCTL_CONFIG EC_IOWR(0x18, ec_ioctl_config_t)
#define EC_IOCTL_CONFIG_PDO_ENTRY EC_IOWR(0x19, ec_ioctl_config_pdo_entry_t) #define EC_IOCTL_CONFIG_PDO EC_IOWR(0x19, ec_ioctl_config_pdo_t)
#define EC_IOCTL_CONFIG_SDO EC_IOWR(0x1a, ec_ioctl_config_sdo_t) #define EC_IOCTL_CONFIG_PDO_ENTRY EC_IOWR(0x1a, ec_ioctl_config_pdo_entry_t)
#define EC_IOCTL_CONFIG_SDO EC_IOWR(0x1b, ec_ioctl_config_sdo_t)
#ifdef EC_EOE #ifdef EC_EOE
#define EC_IOCTL_EOE_HANDLER EC_IOWR(0x1b, ec_ioctl_eoe_handler_t) #define EC_IOCTL_EOE_HANDLER EC_IOWR(0x1c, ec_ioctl_eoe_handler_t)
#endif #endif
// Application interface // Application interface
#define EC_IOCTL_REQUEST EC_IO(0x1c) #define EC_IOCTL_REQUEST EC_IO(0x1d)
#define EC_IOCTL_CREATE_DOMAIN EC_IO(0x1d) #define EC_IOCTL_CREATE_DOMAIN EC_IO(0x1e)
#define EC_IOCTL_CREATE_SLAVE_CONFIG EC_IOWR(0x1e, ec_ioctl_config_t) #define EC_IOCTL_CREATE_SLAVE_CONFIG EC_IOWR(0x1f, ec_ioctl_config_t)
#define EC_IOCTL_ACTIVATE EC_IOR(0x1f, size_t) #define EC_IOCTL_ACTIVATE EC_IOR(0x20, size_t)
#define EC_IOCTL_DEACTIVATE EC_IO(0x20) #define EC_IOCTL_DEACTIVATE EC_IO(0x21)
#define EC_IOCTL_SEND EC_IO(0x21) #define EC_IOCTL_SEND EC_IO(0x22)
#define EC_IOCTL_RECEIVE EC_IO(0x22) #define EC_IOCTL_RECEIVE EC_IO(0x23)
#define EC_IOCTL_MASTER_STATE EC_IOR(0x23, ec_master_state_t) #define EC_IOCTL_MASTER_STATE EC_IOR(0x24, ec_master_state_t)
#define EC_IOCTL_APP_TIME EC_IOW(0x24, ec_ioctl_app_time_t) #define EC_IOCTL_APP_TIME EC_IOW(0x25, ec_ioctl_app_time_t)
#define EC_IOCTL_SYNC_REF EC_IO(0x25) #define EC_IOCTL_SYNC_REF EC_IO(0x26)
#define EC_IOCTL_SYNC_SLAVES EC_IO(0x26) #define EC_IOCTL_SYNC_SLAVES EC_IO(0x27)
#define EC_IOCTL_SYNC_MON_QUEUE EC_IO(0x27) #define EC_IOCTL_SYNC_MON_QUEUE EC_IO(0x28)
#define EC_IOCTL_SYNC_MON_PROCESS EC_IOR(0x28, uint32_t) #define EC_IOCTL_SYNC_MON_PROCESS EC_IOR(0x29, uint32_t)
#define EC_IOCTL_SC_SYNC EC_IOW(0x29, ec_ioctl_config_t) #define EC_IOCTL_SC_SYNC EC_IOW(0x2a, ec_ioctl_config_t)
#define EC_IOCTL_SC_WATCHDOG EC_IOW(0x2a, ec_ioctl_config_t) #define EC_IOCTL_SC_WATCHDOG EC_IOW(0x2b, ec_ioctl_config_t)
#define EC_IOCTL_SC_ADD_PDO EC_IOW(0x2b, ec_ioctl_config_pdo_t) #define EC_IOCTL_SC_ADD_PDO EC_IOW(0x2c, ec_ioctl_config_pdo_t)
#define EC_IOCTL_SC_CLEAR_PDOS EC_IOW(0x2c, ec_ioctl_config_pdo_t) #define EC_IOCTL_SC_CLEAR_PDOS EC_IOW(0x2d, ec_ioctl_config_pdo_t)
#define EC_IOCTL_SC_ADD_ENTRY EC_IOW(0x2d, ec_ioctl_add_pdo_entry_t) #define EC_IOCTL_SC_ADD_ENTRY EC_IOW(0x2e, ec_ioctl_add_pdo_entry_t)
#define EC_IOCTL_SC_CLEAR_ENTRIES EC_IOW(0x2e, ec_ioctl_config_pdo_t) #define EC_IOCTL_SC_CLEAR_ENTRIES EC_IOW(0x2f, ec_ioctl_config_pdo_t)
#define EC_IOCTL_SC_REG_PDO_ENTRY EC_IOWR(0x2f, ec_ioctl_reg_pdo_entry_t) #define EC_IOCTL_SC_REG_PDO_ENTRY EC_IOWR(0x20, ec_ioctl_reg_pdo_entry_t)
#define EC_IOCTL_SC_DC EC_IOW(0x20, ec_ioctl_config_t) #define EC_IOCTL_SC_DC EC_IOW(0x31, ec_ioctl_config_t)
#define EC_IOCTL_SC_SDO EC_IOW(0x31, ec_ioctl_sc_sdo_t) #define EC_IOCTL_SC_SDO EC_IOW(0x32, ec_ioctl_sc_sdo_t)
#define EC_IOCTL_SC_SDO_REQUEST EC_IOWR(0x32, ec_ioctl_sdo_request_t) #define EC_IOCTL_SC_SDO_REQUEST EC_IOWR(0x33, ec_ioctl_sdo_request_t)
#define EC_IOCTL_SC_VOE EC_IOWR(0x33, ec_ioctl_voe_t) #define EC_IOCTL_SC_VOE EC_IOWR(0x34, ec_ioctl_voe_t)
#define EC_IOCTL_SC_STATE EC_IOWR(0x34, ec_ioctl_sc_state_t) #define EC_IOCTL_SC_STATE EC_IOWR(0x35, ec_ioctl_sc_state_t)
#define EC_IOCTL_SC_IDN EC_IOW(0x35, ec_ioctl_sc_idn_t) #define EC_IOCTL_SC_IDN EC_IOW(0x36, ec_ioctl_sc_idn_t)
#define EC_IOCTL_DOMAIN_OFFSET EC_IO(0x36) #define EC_IOCTL_DOMAIN_OFFSET EC_IO(0x37)
#define EC_IOCTL_DOMAIN_PROCESS EC_IO(0x37) #define EC_IOCTL_DOMAIN_PROCESS EC_IO(0x38)
#define EC_IOCTL_DOMAIN_QUEUE EC_IO(0x38) #define EC_IOCTL_DOMAIN_QUEUE EC_IO(0x39)
#define EC_IOCTL_DOMAIN_STATE EC_IOWR(0x39, ec_ioctl_domain_state_t) #define EC_IOCTL_DOMAIN_STATE EC_IOWR(0x3a, ec_ioctl_domain_state_t)
#define EC_IOCTL_SDO_REQUEST_TIMEOUT EC_IOWR(0x3a, ec_ioctl_sdo_request_t) #define EC_IOCTL_SDO_REQUEST_TIMEOUT EC_IOWR(0x3b, ec_ioctl_sdo_request_t)
#define EC_IOCTL_SDO_REQUEST_STATE EC_IOWR(0x3b, ec_ioctl_sdo_request_t) #define EC_IOCTL_SDO_REQUEST_STATE EC_IOWR(0x3c, ec_ioctl_sdo_request_t)
#define EC_IOCTL_SDO_REQUEST_READ EC_IOWR(0x3c, ec_ioctl_sdo_request_t) #define EC_IOCTL_SDO_REQUEST_READ EC_IOWR(0x3d, ec_ioctl_sdo_request_t)
#define EC_IOCTL_SDO_REQUEST_WRITE EC_IOWR(0x3d, ec_ioctl_sdo_request_t) #define EC_IOCTL_SDO_REQUEST_WRITE EC_IOWR(0x3e, ec_ioctl_sdo_request_t)
#define EC_IOCTL_SDO_REQUEST_DATA EC_IOWR(0x3e, ec_ioctl_sdo_request_t) #define EC_IOCTL_SDO_REQUEST_DATA EC_IOWR(0x3f, ec_ioctl_sdo_request_t)
#define EC_IOCTL_VOE_SEND_HEADER EC_IOW(0x3f, ec_ioctl_voe_t) #define EC_IOCTL_VOE_SEND_HEADER EC_IOW(0x40, ec_ioctl_voe_t)
#define EC_IOCTL_VOE_REC_HEADER EC_IOWR(0x40, ec_ioctl_voe_t) #define EC_IOCTL_VOE_REC_HEADER EC_IOWR(0x41, ec_ioctl_voe_t)
#define EC_IOCTL_VOE_READ EC_IOW(0x41, ec_ioctl_voe_t) #define EC_IOCTL_VOE_READ EC_IOW(0x42, ec_ioctl_voe_t)
#define EC_IOCTL_VOE_READ_NOSYNC EC_IOW(0x42, ec_ioctl_voe_t) #define EC_IOCTL_VOE_READ_NOSYNC EC_IOW(0x43, ec_ioctl_voe_t)
#define EC_IOCTL_VOE_WRITE EC_IOWR(0x43, ec_ioctl_voe_t) #define EC_IOCTL_VOE_WRITE EC_IOWR(0x44, ec_ioctl_voe_t)
#define EC_IOCTL_VOE_EXEC EC_IOWR(0x44, ec_ioctl_voe_t) #define EC_IOCTL_VOE_EXEC EC_IOWR(0x45, ec_ioctl_voe_t)
#define EC_IOCTL_VOE_DATA EC_IOWR(0x45, ec_ioctl_voe_t) #define EC_IOCTL_VOE_DATA EC_IOWR(0x46, ec_ioctl_voe_t)
#define EC_IOCTL_SET_SEND_INTERVAL EC_IOW(0x46, size_t) #define EC_IOCTL_SET_SEND_INTERVAL EC_IOW(0x47, size_t)
/*****************************************************************************/ /*****************************************************************************/

85
tool/CommandRescan.cpp Normal file
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@ -0,0 +1,85 @@
/*****************************************************************************
*
* $Id$
*
* Copyright (C) 2006-2009 Florian Pose, Ingenieurgemeinschaft IgH
*
* This file is part of the IgH EtherCAT Master.
*
* The IgH EtherCAT Master is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License version 2, as
* published by the Free Software Foundation.
*
* The IgH EtherCAT Master is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General
* Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with the IgH EtherCAT Master; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*
* ---
*
* The license mentioned above concerns the source code only. Using the
* EtherCAT technology and brand is only permitted in compliance with the
* industrial property and similar rights of Beckhoff Automation GmbH.
*
* vim: expandtab
*
****************************************************************************/
#include <sstream>
#include <iomanip>
using namespace std;
#include "CommandRescan.h"
#include "MasterDevice.h"
/*****************************************************************************/
CommandRescan::CommandRescan():
Command("rescan", "Rescan the bus.")
{
}
/*****************************************************************************/
string CommandRescan::helpString() const
{
stringstream str;
str << getName() << endl
<< endl
<< getBriefDescription() << endl
<< endl
<< "Command a bus rescan. Gathered slave information will be" << endl
<< "forgotten and slaves will be read in again." << endl
<< endl;
return str.str();
}
/****************************************************************************/
void CommandRescan::execute(const StringVector &args)
{
MasterIndexList masterIndices;
if (args.size() != 0) {
stringstream err;
err << "'" << getName() << "' takes no arguments!";
throwInvalidUsageException(err);
}
masterIndices = getMasterIndices();
MasterIndexList::const_iterator mi;
for (mi = masterIndices.begin();
mi != masterIndices.end(); mi++) {
MasterDevice m(*mi);
m.open(MasterDevice::ReadWrite);
m.rescan();
}
}
/*****************************************************************************/

49
tool/CommandRescan.h Normal file
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@ -0,0 +1,49 @@
/*****************************************************************************
*
* $Id$
*
* Copyright (C) 2006-2009 Florian Pose, Ingenieurgemeinschaft IgH
*
* This file is part of the IgH EtherCAT Master.
*
* The IgH EtherCAT Master is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License version 2, as
* published by the Free Software Foundation.
*
* The IgH EtherCAT Master is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General
* Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with the IgH EtherCAT Master; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*
* ---
*
* The license mentioned above concerns the source code only. Using the
* EtherCAT technology and brand is only permitted in compliance with the
* industrial property and similar rights of Beckhoff Automation GmbH.
*
****************************************************************************/
#ifndef __COMMANDRESCAN_H__
#define __COMMANDRESCAN_H__
#include "Command.h"
/****************************************************************************/
class CommandRescan:
public Command
{
public:
CommandRescan();
string helpString() const;
void execute(const StringVector &);
};
/****************************************************************************/
#endif

2
tool/Makefile.am
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@ -52,6 +52,7 @@ ethercat_SOURCES = \
CommandPdos.cpp \ CommandPdos.cpp \
CommandRegRead.cpp \ CommandRegRead.cpp \
CommandRegWrite.cpp \ CommandRegWrite.cpp \
CommandRescan.cpp \
CommandSdos.cpp \ CommandSdos.cpp \
CommandSiiRead.cpp \ CommandSiiRead.cpp \
CommandSiiWrite.cpp \ CommandSiiWrite.cpp \
@ -93,6 +94,7 @@ noinst_HEADERS = \
CommandPdos.h \ CommandPdos.h \
CommandRegRead.h \ CommandRegRead.h \
CommandRegWrite.h \ CommandRegWrite.h \
CommandRescan.h \
CommandSdos.h \ CommandSdos.h \
CommandSiiRead.h \ CommandSiiRead.h \
CommandSiiWrite.h \ CommandSiiWrite.h \

11
tool/MasterDevice.cpp
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@ -455,6 +455,17 @@ void MasterDevice::setDebug(unsigned int debugLevel)
/****************************************************************************/ /****************************************************************************/
void MasterDevice::rescan()
{
if (ioctl(fd, EC_IOCTL_MASTER_RESCAN, 0) < 0) {
stringstream err;
err << "Failed to command rescan: " << strerror(errno);
throw MasterDeviceException(err);
}
}
/****************************************************************************/
void MasterDevice::sdoDownload(ec_ioctl_slave_sdo_download_t *data) void MasterDevice::sdoDownload(ec_ioctl_slave_sdo_download_t *data)
{ {
if (ioctl(fd, EC_IOCTL_SLAVE_SDO_DOWNLOAD, data) < 0) { if (ioctl(fd, EC_IOCTL_SLAVE_SDO_DOWNLOAD, data) < 0) {

1
tool/MasterDevice.h
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@ -132,6 +132,7 @@ class MasterDevice
void readReg(ec_ioctl_slave_reg_t *); void readReg(ec_ioctl_slave_reg_t *);
void writeReg(ec_ioctl_slave_reg_t *); void writeReg(ec_ioctl_slave_reg_t *);
void setDebug(unsigned int); void setDebug(unsigned int);
void rescan();
void sdoDownload(ec_ioctl_slave_sdo_download_t *); void sdoDownload(ec_ioctl_slave_sdo_download_t *);
void sdoUpload(ec_ioctl_slave_sdo_upload_t *); void sdoUpload(ec_ioctl_slave_sdo_upload_t *);
void requestState(uint16_t, uint8_t); void requestState(uint16_t, uint8_t);

2
tool/main.cpp
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@ -52,6 +52,7 @@ using namespace std;
#include "CommandPdos.h" #include "CommandPdos.h"
#include "CommandRegRead.h" #include "CommandRegRead.h"
#include "CommandRegWrite.h" #include "CommandRegWrite.h"
#include "CommandRescan.h"
#include "CommandSdos.h" #include "CommandSdos.h"
#include "CommandSiiRead.h" #include "CommandSiiRead.h"
#include "CommandSiiWrite.h" #include "CommandSiiWrite.h"
@ -307,6 +308,7 @@ int main(int argc, char **argv)
commandList.push_back(new CommandPdos()); commandList.push_back(new CommandPdos());
commandList.push_back(new CommandRegRead()); commandList.push_back(new CommandRegRead());
commandList.push_back(new CommandRegWrite()); commandList.push_back(new CommandRegWrite());
commandList.push_back(new CommandRescan());
commandList.push_back(new CommandSdos()); commandList.push_back(new CommandSdos());
commandList.push_back(new CommandSiiRead()); commandList.push_back(new CommandSiiRead());
commandList.push_back(new CommandSiiWrite()); commandList.push_back(new CommandSiiWrite());